Titre :	Verilog styles for synthesis of digital systems
Type de document :	texte imprime
Auteurs :	David R. Smith, Auteur ; Paul D. Franzon, Collaborateur
Editeur :	Englewood Cliffs : Prentice Hall
Année de publication :	N.J.
Importance :	(XIV-314 p.)
Présentation :	ill., couv. ill. en coul.
Format :	25 cm
ISBN/ISSN/EAN :	978-0-201-61860-0
Note générale :	Bibliogr. en fin de chapitres. Index
Langues :	Anglais
Mots-clés :	Réseaux logiques programmables par l'utilisateur:conception assistée par ordinateur  Verilog (langage de description de matériel informatique)  Field programmable gate arrays:computer-aided design  Verilog (Computer hardware description language)
Index. décimale :	621.395
Résumé :	For senior/graduate-level courses in Digital Hardware Design/Verilog. This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students―e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester. The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester. Features: The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader. It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation. Large number of examples; from 100-100k gate equivalents. Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.
Permalink :	./index.php?lvl=notice_display&id=10710

Verilog styles for synthesis of digital systems [texte imprime] / David R. Smith, Auteur ; Paul D. Franzon, Collaborateur . - Englewood Cliffs : Prentice Hall, N.J. . - (XIV-314 p.) : ill., couv. ill. en coul. ; 25 cm.
ISBN : 978-0-201-61860-0
Bibliogr. en fin de chapitres. Index
Langues : Anglais

Mots-clés :	Réseaux logiques programmables par l'utilisateur:conception assistée par ordinateur  Verilog (langage de description de matériel informatique)  Field programmable gate arrays:computer-aided design  Verilog (Computer hardware description language)
Index. décimale :	621.395
Résumé :	For senior/graduate-level courses in Digital Hardware Design/Verilog. This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students―e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester. The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester. Features: The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader. It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation. Large number of examples; from 100-100k gate equivalents. Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.
Permalink :	./index.php?lvl=notice_display&id=10710